Code compression system

ABSTRACT

A code compression system comprises a generator for producing a maximal length sequence code at a first predetermined frequency. The code is delayed with respect to the generated code, and both codes are then combined to produce an output code having an identical maximal length sequence code as the generated code, at a higher multiple frequency than the generated code. The circuit for combining the generated code and the delayed code may comprise an exclusive OR gate.

United States Patent DELQV 15] 3,657,718 OFarrell [4s 1 Apr. 18, 1972[541 CODE COMPRESSION SYSTEM 3,069,657 12/ 1962 Green et al. ..340/146.1 1 3,518,547 6/1970 Filipowsky ..l79/ 150 R X [72] Invent 0Sepulveda' 3,155,818 11/1964 Goetz ..340/l46.l x {73] Assignee:International Telephone and Telegraph 'p t New York, PrimaryExaminer-Thomas A. Robinson Attorney-C. Cornell Remsen, Jr., Walter J.Baum, Paul W. [22] Flled' June 1970 l-lemmin er and Thomas E.Kristofi'erson [21] A IN 50628 g [57] ABSTRACT v U.S. DD, A codecompression ystem comprises a generator for produc. [51] Int. Cl..l-l03r 13/32, H03r 13/00 ing a i l length sequence code at a firstpredetermined [58] Field of Search ..340/347 DD, 348, 35 I, 355:frequency The code is delayed with respect to the generated 340/ 6328/32 code, and both codes are then combined to produce an output307/271 325/38 178/66 23 235/154 code having an identical maximal lengthsequence code as the generated code, at a higher multiple frequency thanthe [56] References cued generated code. The circuit for combining thegenerated code UNITED STATES PATENTS and the delayed code may comprisean exclusive OR gate. 3,105,955 10/1963 Mauchly ..340/ 146.1 3 Claims, 7Drawing Figures 38 4 52, I2; 5e 58 eq 607p DELRY Patented April 18, 19722 Sheets-Sheet 2 BY KM FITTORA/(EY BACKGROUND OF THE INVENTION ofsampled Prior art high frequency codes have been produced by directlygenerating the high frequency code from a clock source, which hasrequired the use of very fast adders and shift registers. Alternatively,high frequency sampling has been utilized to produce high frequencycodes which utilized state eof the art coders. A typical high frequencysampler is described in US. Pat. application Ser. No. 885,087 filed Dec.15, I969 and assigned to the assignee of the present application. Theaforementioned patent application produces a maximal length sequencecode at a multiple frequency of an input maximal length sequence code.The input maximal length sequence codes are provided at a predetenninedfrequency and are delayed by a fixed amount with respect to each other.The codes are sampled at a rate higher than the frequencies of thecodes. The sample codes are then combined to produce the output code ata multiple of the input frequency.

In order to overcome the attendant disadvantages of prior art codefrequency compressors, the present invention eliminates the need fordirect generation of the code using high frequency'clock sources.Moreover, high frequency sampling of the. input codes is not required.By delaying the input code utilizing conventional delay techniques andadding the delay code to the input code the input code can be compressedso that a high frequency code is generated. Moreover, state of the artcomponents can be utilized in the system.

The advantages of this invention, both as to its construction and modeof operation will be readily appreciated as the same becomes betterunderstood by reference to the following detailed description whenconsidered in connecting with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS DESCRIPTION OF THE PREFERREDEMBODIMENT In describing the apparatus of the present invention, aconvention is employed wherein an exclusive OR gate is shown as Inputsare applied to the exclusive OR gate at the left and an output appearson the right. In'the present case, an exclusive OR gate produces anoutput signal C in accordance with the following formula: C A F B Awhere A and B are inputs to the exclusive OR gate.

Referring now to FIG. I of the drawings, thereis sown a schematic blockdiagram of a preferred embodiment of the apparatus of the presentinvention. The code compression system of FIG. 1 contains a shiftregister 12 which has n stages with proper interstage feedbackconnections and is driven by a clock 14. The output of the shiftregister 12 is a linear maximal sequence of L 2" 1 bits length.

. z As described in Us. Pat. application Set. No. 885,087 filed Dec. 15,1969, a linear maximal sequency is a binary sequence generated by alinear shift register generator and which has the longest possible wordlength period for this generation method. This longest possible periodis given by the fonnula where L equals the length of the maximal lengthsequence;

and n equals the number of stages in the shift register, and f equalsthe clock frequency.

The present invention describes a method and apparatus by which codewords of a repetition period L/Kf= 2'"- 1/10 can be generated withouthigher frequency clocks or sampling devices. It has been found that eachidentical K number of codes at clock frequency f with proper relativedelays are sequentially added in binary fashion by use of an exclusiveOR gate and a compressed code of clock frequency Kf is obtained.

Thus, referring once again to FIG. 1, an exclusive OR gate 16 has oneinput tenninal connected to the output of the shift register 12.Further, the output of the shift register 12 is also connected to adelay network 18 having a delay L/2 f. The output of the delay networkis coupled to another input terminal of the exclusive OR gate 16 whoseoutput is coupled to the output tenninal 22.

Referring now to FIG. 2, there are shown in FIG. 2a the clock pulses ata clock frequency f which are coupled to the input of the shift register12. The output of the shift register is shown in FIG. 2b and comprises amaximal length sequency which is coupled to one of the inputs of theexclusive OR gate 16. Further, this maximal length sequence of FIG. 2ais coupled to the delay network 18 whose output, shown in FIG. 20comprises a one-half word delayed code. FIG. 2d depicts the output ofthe exclusive OR gate 16 which is produced at terminal 22. As can bereadily seen, the output at terminal 22 is a maximal length code whichis twice the frequency of the code of FIG. 2b.

' As shown with respect to FIG. 1 and 2, for K 2, the relative delayis'one-half word and the binary sequence consists of a single addition.For K 3, the relative delay is one-third word and two additions-arerequired, namely the zero delayed code with the one-third word delayedcode and then, the resultant of this addition with the two-thirds worddelayed code. 1

Referring now to FIG. 3, there is illustrated a block diagram of thecode compression system for the condition where K 3. A clock ,l4'iscoupled to a shift register 12 both of which may be similar to that ofFIG. I. The output of the shift register is coupled to an input terminalof a first exclusive OR gate 24 and to a delay network 26 having a delayof one-third word. The output of the delay network 26 is coupled to theother input terminal of the exclusive OR gate 24. Further, the output ofthe shift register is coupled to a second delay network 28 which delaysthe code two-thirds of a word. The output of the gate 24, as well as theoutput of the delay network 28 are each coupled to input terminals of anexclusive OR gate 29, respectively. The output of the gate 29 is coupledto an output terminal 30.

FIG. 4 (a. through f) depicts the waveform for K 3. FIG. 4 (a) depictsthe clock pulses having a frequency coupled from the clock 14 toregister 12 which code depicted in FIG. 4 (b). FIG. 4 (c) depicts themaximal length code of FIG. 4 (b) delayed one-third word by the delaynetwork 26. Use of the exclusive OR gate 24 to perform binary additionto the codes of FIGS. 4 (b) and 4 (0) results in the binary sum shown inFIG. 4 (d). Further, the code of FIG. 4 (b) is delayed two-thirds of aword by delay 28 as shown in FIG. 4(a) and the binary sum of FIG. 4 (d)4 (e) are then binary added together to produce a binary sum shown inFIG. 4

Q). As can be readily seen, the code of FIG. 4 (f) has a repetition rateof three times the frequency of the code of FIG. 4 (b).

For K 4, it is possible to obtain the detailed code by two K 5 2operations which require two delays and two additions.

produces a maximal length' Further, thestraightforward application ofone-fourth word 1 delays requires three delays and three additions. Ingeneral,

a the number of delays and additions required are always equal and canbe computed by factoring K into its primitive factors of I a=2a3e5c7d.....

where a, b, c, d are the number of times the respective factor isrepeated which then establishes thenumber of required delays oradditions Q as Q=a+2b+4c+6d+.....

It must be noted that Kvmay assume any value, except those thatarefactors of L.

The only high frequency device required for the present in-* vention arethe binary adders of the final multiplication series which must respondwith sufficient speed to allow variation of pulses UK of the width ofthe original wave form pulses. The relative. delay required between basefrequency codes is unique and not other delay or combination of delayswill pro vide the desired results.

Referring nowto FIGS. 5. through 7, there are shown three alternate waysof generating a code having a frequency of 60 cation required. For K 60the number of steps equals four (2 X2 X 3 X 5).

The first step is a multiplication by 2 and therefore requires arelative delay of one-half the periodof the f frequency code L'/ 2 f toproduce the compressed code of frequency 2 f.

The second step is a multiplication by 2 of the 2 f frequency codeandtherefore requires a relative delay of one-half the code and, therefore,requires two relative delays of one-third the period of the 4 ffrequency code or one-third (L/4f) and two-thirds the period oftwo-thirds L/4f).

The fourth step is a multiplication by 5 of the 12 f frequency a codeand therefore requires four relative delays of one-fifth or 1/5 (L/12f),two-fifths or 2/5 (L/ 12)), three-fifths or 3/5 (L/ 12f and four-fifthsor 4/5 (L/ 12]), the period of the 12 f frequency code. The combinedaddition then yields acompressed code of clock frequency 60 f with only8 delay elements. The straightforward approach wouldrequire 59 delayseach spaced L/60 f or one-sixtieth of a code word interval apart. a

More particularly, in FIG. 5, the shift register 12 couples a maximallength code such as that depicted in FIGS. 1 through 4 to one of theinput terminals of an exclusive OR circuit 34 as well as to a delaynetwork 36 having a delay L/2f. The output of the delay network 36 isalso coupled to an input terminal of the exclusive OR gate 34, and, aswas previously explained with respect to the circuit of FIGS. 1 and 2,an output is present at the output of the exclusive OR gate 34 whosefrequency is twice that of the input code to the circuit 34. This,output signal is then coupled to a second exclusive OR gate 38 as wellas through a delay network 42 having a delay one-half that of the delaynetwork 36. The output code at the output of the exclusive OR gate 38will be, of course, twice the frequency as the code coupled to the inputof gate 34.

Thecode at the output of gate 38 may then be, as in the technique shownin FIGS. 3 and 4, coupled to a first input terminal of an exclusive ORgate 44 as well as through a onethird word delay 46 to another inputterminal of the exclusive OR gate 44. Further, the input signal iscoupled through a twothirds word delay 48 to an input terminal of anexclusive OR gate 52. The outputsignal at the OR gate 44 is also coupledto the other input terminal of the gate 52. The resultant output at theexclusive OR gate 52 will be a code having a frequency 1 times thefrequency of theinitial code generated bythe shift register or threetimes the frequency of the code at the output of the exclusive OR gate38.

Moreover, this compressed code is coupled to the input and outputterminals of exclusive OR gates 54, 56, 58 and 60 as well as'throughcode word delays produced by networks 62, 64, 66 and 68, respectively,and hence into the other input terminal of the gates 54, 56, 58 and 60,respectively. Finally, the output at an output terminal of the gate 60will be five times the input frequency at the gate or 60 times the inputfrequency of the code generated by the shift register.

An alternate way of generating the required delays, keeping in mind thathardware weight and volume increase as the delay increases, is toarrange the delays in series. For instance, four delays of one-fifthword will provide a total delay of fourfifths. FIG. 6 shows thisalternate arrangement wherein four delays 72, 74, 76 and 78 of U5(U12 1) connected in series replace the delays 62, 64, 66 and 68 ofFlG,5. i

For the code described in' FIG. 6 for a starting clock frequencyf= 1.67MHz and n 3 or L 2" l 7, the individual delay types required for the 60f code MHz) are as follows:

Delay nesis'asaBinariesirageaeaasr; an; sweats using the lowest valued Kfactors first and then increasing the multiplication process (2 X 2 X 3X 5). The largest delay required is L/2 f or 2.1 11. sec. By reversingthe multiplication factors the largest delay required can besignificantly reduced. FIG. 8 shows the delays required. It is notedthat the largest delay is US for 0.84 a see which is two and one-halftimes lower than that required for FIG. 6.'Therefore, to keep the amountof delay at a minimum the highest order K factors should be used first.Also, the order of multiplication (highest factor first) requires aminimum number of fast gates. For the code depicted in FIG. 7 and thesame starting clock frequency, f 1.67 MHz and code length L 7, are thatof FIG. 7 the individual delay types required for the 60 f code (100MHz) are as follows:

Delay In FIG. 7, four gates, 82, 84, 86 and 88 are connected in seriescombination with delay networks 92, 94, 96 and 98, respectively, thefour delays having a delay of U5 f. Thus, the resultant output at theexclusive OR gate 88 is a compressed code of frequency 5f.

The output signal at the gate 88 is then again utilized as an input to apair of series connected delays 102 and 104, each of which provides aone-third word delay for the output signal from the gate 88. The outputsignal from the gate 88 together with the output from the delay 102 arecoupled to an exclusive OR gate 106. The output of gate 106, togetherwith the output signal from the delay 104 are coupled to an exclusive ORgate 108. The output code at the gate 108 has a frequency three timesthe output code of the gate 88, or times the original code. Then theoutput signal from gate 108 is coupled to one input terminal of anexclusive OR gate 112 and through a delay 114 having one-half code worddelay. The output of the delay 114 is coupled to the other inputterminal of the gate 112 with the resultant output frequency being twicethe input frequency to the gate 112. Finally, in order to produce a codeword having an output frequency 60 times the input frequency, the delayof gate 112 is coupled to still another OR gate 116 and through a delay118 having a delay one-half code word for the signal from the output ofgate 112. This, of course, results in an output code word at the outputof gate 116 having a frequency equal to 60 times the input frequency tothe system.

In summary, the novel method of code compression described herein allowsthe basic coder circuitry to operate at a lower speed and only theexclusive OR gates need operate at the higher speeds. Speeds of gatecircuits are inherently faster than flip flops, shift registers in thatthese latter elements are made up of multiple gate circuits.

It should be further understood that other alternative arrangements forproducing multiple frequency codes with respect to an input frequencycode are possible with the illustrations provided in the drawings beingmerely typical and not limiting.

What is claimed is:

1. A code compression system comprising:

means for generating a first maximal length sequence code at apredetennined frequency;

means for producing a second maximal length sequence code at saidpredetermined frequency having a'wavefonn identical to said firstmaximal length sequence code, said second maximal length sequence codebeing delayed a predetermined interval with respect to said firstmaximal length sequence code; and

means for producing a maximal length sequence code identical to saidfist and second maximal length sequence codes at a frequency higher thansaid predetennined frequency comprising an exclusive OR gate having afirst input terminal and a second input terminal, said first and secondmaximal length sequence codes being coupled to said first and secondinput terminals, respectively.

2. A code compression system in accordance with claim 1 wherein saidmeans for producing said second maximal length sequence code comprises adelay network having a delay D, where D L/Kf where L=the length of themaximal length sequence;

f the clock frequency of the maximal length sequence;

and

K the number of codes at clock frequency f which must be added to obtaina compressed code of clock frequency K 3. A code compression system inaccordance with claim 2 wherein the input to said delay network is saidfirst maximal length sequence code.

1. A code compression system comprising: means for generating a firstmaximal length sequence code at a predetermined frequency; means forproducing a second maximal length sequence code at said predeterminedfrequency having a waveform identical to said first maximal lengthsequence code, said second maximal length sequence code being delayed apredetermined interval with respect to said first maximal lengthsequence code; and means for producing a maximal length sequence codeidentical to said fist and second maximal length sequence codes at afrequency higher than said predetermined frequency comprising anexclusive OR gate having a first input terminal and a second inputterminal, said first and second maximal length sequence codes beingcoupled to said first and second input terminals, respectively.
 2. Acode compression system in accordance with claim 1 wherein said meansfor producing said second maximal length sequence code comprises a delaynetwork having a delay D, where D L/Kf where L the length of the maximallength sequence; f the clock frequency of the maximal length sequence;and K the number of codes at clock frequency f which must be added toobtain a compressed code of cloCk frequency Kf.
 3. A code compressionsystem in accordance with claim 2 wherein the input to said delaynetwork is said first maximal length sequence code.